low-power logic
英 [ləʊ ˈpaʊə(r) ˈlɒdʒɪk]
美 [loʊ ˈpaʊər ˈlɑːdʒɪk]
低功率逻辑
双语例句
- Low-Power Non-full Swing Complementary Pass-Transistor Logic Adder
低功耗非全摆幅互补传输管加法器 - In this paper a low-power dynamic ternary CMOS D flip-flop was designed, which is based on the dynamic CMOS ternary inverter having full voltage swings without DC power dissipations and is combined with the structure of a Simple Ternary Differential Logic ( STDL).
本文以一种没有直流功耗，具有完全电压摆幅的低功耗动态CMOS三值反相器作为基础，结合简单三值差分逻辑（STDL）的结构，设计了一种低功耗动态三值CMOSD触发器。 - An FBAR tiny-mass sensor signal acquisition and processing chip is designed, fabricated, and tested. Low-power source-coupled logic dividers are introduced to reduce the frequency of RF signals from Giga Hertz to a frequency that CMOS circuit could deal with. 3.
设计、流片并测试了该FBAR微质量传感信息采集处理的芯片，该芯片前级采用低功耗的源耦合逻辑分频器对射频信号进行预分频。